Editing ModelingState in

Title: ModelingState in

Main Research Question: How can we develop a model-based diagnosis approach for debugging VHDL-RTL designs that effectively localizes faults and supports the temporal behavior of sequential circuits?

Methodology: The authors propose an approach to apply model-based diagnosis to the field of automatic software debugging of hardware designs. They present their value-level model for debugging VHDL-RTL designs and demonstrate how to localize the erroneous component responsible for an observed misbehavior. Furthermore, they discuss an extension of their model that supports the debugging of sequential circuits, allowing for consideration of both the current state and the temporal behavior of VHDL-RTL designs.

Results: The authors use industrial-sized real-world examples from the ISCAS'85 benchmark suite to discuss the scalability of their approach. They provide empirical results that demonstrate the effectiveness of their model in localizing faults and supporting the temporal behavior of sequential circuits.

Implications: The introduced model is capable of handling state inherently present in sequential circuits. The principal applicability of the new model is outlined briefly, and the authors believe that it has the potential to revolutionize the field of automatic software debugging of hardware designs.

Link to Article: https://arxiv.org/abs/0311001v1
Authors: 
arXiv ID: 0311001v1

[[Category:Computer Science]]
[[Category:Model]]
[[Category:Debugging]]
[[Category:Designs]]
[[Category:Sequential]]
[[Category:Circuits]]