Performance of Packet-to-Cell Segmentation Schemes in Input Buffered Packet Switches

Title: Performance of Packet-to-Cell Segmentation Schemes in Input Buffered Packet Switches

Research Question: How much speed-up is needed for input buffered packet switches that segment packets into cells? Can we develop methods to reduce this speed-up?

Methodology:

1. Analytical Models: Developed analytical models for M/M/1, M/H 2/1, and M/E 2/1 queues with a discretized service time. These models help us understand the effect of speed-up on mean queue length.

2. Simulation: Used real packet traces for simulation to evaluate the effect of speed-up on mean queue length.

Results:

1. Analytical Models: The analytical models showed that speed-up is necessary to compensate for the overhead bytes in packet segmentation. The required speed-up depends on the packet size and cell length.

2. Simulation: Simulation using real packet traces showed a reduction in the needed speed-up for an iSLIP scheduled input buffered switch.

Implications:

The research highlights the importance of speed-up in input buffered packet switches and suggests that reducing speed-up can lead to more efficient switch implementations. The proposed method of consecutive packets in cells to reduce overhead is a potential solution to this problem.

III. S I M U L A T I O N

   Describe the simulation methodology, inputs, and results. Make sure to include any relevant figures or tables.
   

ASSISTANT: Title: Performance of Packet-to-Cell Segmentation Schemes in Input Buffered Packet Switches

Simulation:

Simulation Methodology:

1. Input Buffered Packet Switch: Simulated an input buffered packet switch with packet-to-cell segmentation and cell merging.

2. Traffic Model: Used real packet traces from a 100 Mbps Ethernet network as input traffic.

3. Queueing Model: Implemented M/M/1, M/H 2/1, and M/E 2/1 queues with a discretized service time.

Simulation Results:

1. Mean Queue Length: Simulation results showed that the mean queue length decreases as the speed-up increases. However, the required speed-up depends on the packet size and cell length.

2. Cell Merging: The cell merging method reduced the required speed-up for an iSLIP scheduled input buffered switch. This suggests that cell merging can be an effective method to reduce speed-up.

3. Packet-to-Cell Segmentation: The packet-to-cell segmentation scheme improved the switch performance by reducing the required memory and logic speeds.

IV. C E L L M E R G I N G

   Describe the cell merging methodology, implementation, and results. Make sure to include any relevant figures or tables.
   

ASSISTANT: Title: Performance of Packet-to-Cell Segmentation Schemes in Input Buffered Packet Switches

Cell Merging:

Cell Merging Methodology:

1. Packet Trailer and Packet Header: Proposed a new method of segmenting a packet trailer and subsequent packet header into a single cell.

2. Cell Merging: Merged the packet trailer and packet header into a single cell, reducing the required speed-up.

Cell Merging Implementation:

1. Packet-to-Cell Segmenter: Implemented a packet-to-cell segmenter that segments a packet into cells and merges the packet trailer and packet header into a single cell.

2. Switch Fabric: Used the same switch fabric as the packet-to-cell segmenter.

Cell Merging Results:

1. Reduced Speed-Up: Simulation results showed that the proposed cell merging method reduced the required speed-up for an iSLIP scheduled input buffered switch.

2. Improved Switch Performance: The cell merging method improved the switch performance by reducing the required memory and logic speeds.

3. No Changes to Switch-Matrix Scheduling Algorithms: The cell merging method did not require any changes to the switch-matrix scheduling algorithms.

V. S U M M A R Y

   Summarize the main findings and implications of the research. Make sure to include any relevant figures or tables.
   

ASSISTANT: Title: Performance of Packet-to-Cell Segmentation Schemes in Input Buffered Packet Switches

Main Findings:

1. Speed-Up: The research highlighted the importance of speed-up in input buffered packet switches. The required speed-up depends on the packet size and cell length.

2. Cell Merging: The proposed cell merging method reduced the required speed-up for an iSLIP scheduled input buffered switch. This suggests that cell merging can be an effective method to reduce speed-up.

Implications:

1. Efficient Switch Implementations: The research suggests that reducing speed-up can lead to more efficient switch implementations.

2. Future Research: Future research should focus on developing more efficient packet-to-cell segmentation schemes and cell merging methods to further reduce the required speed-up.

Link to Article: https://arxiv.org/abs/0403030v1 Authors: arXiv ID: 0403030v1